PRR

Back Home Next

horizontal rule

                                    ALICE TPC Front End Electronics

horizontal rule

 

AGENDA
DOCUMENTATION

Review of the Front-End Electronics for the ALICE TPC

CERN, September 09, 2002

Three main components of the FEE for the ALICE TPC are entering the production phase in the next 6 month:

bulletPreamplifier / Shaping Amplifier Chip (PASA)
bullet16-channel ADC and digital processor chip (ALTRO)
bullet128-channel Front End Card (FEC)

The review will mainly focus on these three components. The  design requirements and specifications, the characterization of the final design and the organization of the production and testing will be presented. However, in order to better assess the system level aspects related to the implementation of the above-mentioned components, the overall TPC electronics will be presented, including the components not yet finalized (Readout Network, Control Network and Readout Control Unit).   

Referees

bulletFred Bieser (LBL)
bulletAlessandro Marchioro (CERN)
bulletWalter Mueller (GSI)

 

 
 
 
 
 
 
For problems or questions regarding this web contact Luciano.Musa@cern.ch.

Last update 09/13/2007