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                                    ALICE TPC Front End Electronics

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The table below lists various version of the programming file of the RCU Xilinx FPGA. All these files are variations of an "old" version of the RCU firmare,  refereed as version RCU 1.0.   

Name of the project (.bit file)

(.zip file)

RCU firmware version register

date last modification Notes Registers / Commands Table
RCU_150405   not implemented 15.04.05 RCU version for the XILINX xc2vp4 (PCB ID: 40020152) *
RCU_070705_PHOS   not implemented 27.09.05 S1(F18) or S2 (G18) for the external trigger (L1 aux).

The CSWs are shifted for the PHOS hardware address

RCU_030506   030506


05.05.06 Trigger Module (Bergen) included.

SCLK generated with the PLL

RCU_040506   040506


04.05.06 Trigger Module (Bergen) included.

SCLK generated with a divider (without bunch crossing reset)

RCU_100506   100506 10.05.06 The Slow Control commands have been modified in order to increase the number of bits for the BC register addresses (up to 8 bits). The command Cxxx has been replaced by two registers (0x8002 and 0x8003) and one command (0x8010). A new register (0x8009) defines how the card switch lines are selected (PHOS/TPC). By default, this bit is set to 0 (TPC). .pdf
RCU_190606   190606   Last firmware version. Currently used in the TPC .pdf
RCU_270606   270606 27.06.06 L1_aux has been connected to S2 (G18) .pdf
RCU_091106   061106 10.11.06 Internal clock and RCLK working at 20 MHz (SCLK = 10 MHz)

L1_aux connected to S2 (G18)

RCU_181206   181206 18.12.06 Same version than RCU_270606.

The modification refers to the reset. See Table 1.1 of the Registers/Commands Table.


* contact Roberto Campagnolo (Roberto.Campagnolo@cern.ch, +41 76 487 3494)

For problems or questions regarding this web contact Luciano.Musa@cern.ch.

Last update 09/13/2007